Nasdaq

Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its PHY and Controller IP for the PCI Express® (PCIe®) 5.0 specification in the TSMC N7, N6 and N5 ...
EDN

PCI Express x1 PHY supports source synchronous and DDR clocking

Dallas, Tex.— Texas Instruments Inc.'s PCI Express (PCIe) x1 physical layer (PHY) chip has hit the market in volume, providing a low-cost PCI Express endpoint device for a wide variety of sectors such ...
EDN

Structured ASIC devices embed PCI Express physical layer

Silicon-proven PCIe Subsystem Offers High Performance, Low Risk Alternative to Traditional ASIC, FPGA Options Santa Clara, Calif.—ChipX, the Structured ASIC leader, today announced the CX6100 family ...
Nasdaq

Media Alert: Rambus to Demo 64G PCIe 6.0 PHY and Controller IP at PCI-SIG Developers Conference in Santa Clara, CA

Join us for the PCI-SIG Developers Conference in Santa Clara, CA and see demos of the latest Rambus PCI Express® (PCIe®) 6.0 IP solutions, including 64 Gigatransfers per second (GT/s) PCIe 6.0 PHY and ...
Business Wire

Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance Data Center and AI SoCs

Delivers data rate of up to 64 GT/s for high-performance workloads Supports the full feature set of PCIe 6.0 with PHY support for CXL 3.0 Offers complete IP solution optimized for latency, power, and ...
Semiconductor Engineering

Leveraging Multi-Protocol PHY For PCIe To Cope With SoC Design Complexity

How a refined and enhanced PCIe multi-protocol PHY IP block can pave the way to a new approach in SoC architecture and planning. January 26th, 2022 - By: Cadence Now in the post-Moore’s Law era, the ...
Semiconductor Engineering

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This ...
Design-Reuse

Synopsys Releases Silicon Proven 5.0 Gbps PCI Express 2.0 PHY IP

New DesignWare PHY IP Provides Designers with Complete, Single Vendor IP Solution for the PCI Express 2.0 Interface MOUNTAIN VIEW, Calif. -- April 28, 2008 -- Synopsys, Inc. (NASDAQ: SNPS), a world ...
SiliconANGLE

Synopsys debuts ‘first complete’ chip blueprint bundle for implementing PCIe 7.0

Synopsys Inc. today introduced a suite of hardware designs that chipmakers can use to integrate the PCIe 7.0 interconnect technology into their products. According to the company, the suite is the ...
Electronic Design

PHY/FPGA Duo Provides Low-Cost PCI Express Platform

Pairing the PX1011A PCI Express PHY from Royal Philips Electronics with a Xilinx Spartan-3 XC3S1200E FPGA yields what is unveiled as the first low-cost, programmable PCI Express endpoint silicon ...
Electronic Design

SiPro PCI Express PHY IP Is Production Proven

Designers now have access to silicon and volume production-proven 40-nm G PCI Express Gen1/Gen2 Physical Layer (PHY) intellectual property (IP). The SiPro PCI Express PHY product line is the first ...